CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test (Frontiers in Electronic Testing, 40)
by Andrei Pavlov, Manoj Sachdev
This technical volume explores CMOS SRAM circuit design and parametric testing in nano-scaled technologies. With an emphasis on process-aware SRAM design, it brings together material on memory circuits, semiconductor processes, and electronic testing for readers studying or working in advanced electronic design and test.
About This Book
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies examines SRAM design and testing in advanced semiconductor technologies.
The book focuses on process-aware SRAM design, connecting circuit considerations with the characteristics of nano-scaled manufacturing processes.
It also addresses parametric testing, offering technical coverage relevant to evaluating SRAM behavior and performance.
Published as volume 40 in the Frontiers in Electronic Testing series, this work is intended for readers seeking specialized material on electronic testing and memory circuit design.
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