Introduction to Logic Synthesis Using Verilog HDL (Synthesis Lectures on Digital Circuits and Systems, 6) (Volume 0)
This introductory volume explores logic synthesis using Verilog HDL, placing the subject within the broader context of digital circuits and systems. It offers a focused foundation for students, engineers, and readers developing familiarity with hardware description and digital design concepts.
About This Book
Introduction to Logic Synthesis Using Verilog HDL presents an introductory treatment of logic synthesis using the Verilog hardware description language.
The book is part of the Synthesis Lectures on Digital Circuits and Systems series and focuses on topics connected to digital circuit and system design.
It is intended for readers seeking foundational coverage of the relationship between hardware description and synthesized digital logic.
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